********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Apr 14, 2014
*ECN S14-0791, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiR472ADP D G S 
M1 3 GX S S NMOS W= 2655000u L= 0.25u 
M2 S GX S D PMOS W= 2655000u L= 0.17u
R1 D 3 6.0138e-03 3.874e-03 9.097e-06 
CGS GX S 5.795e-10 
CGD GX D 5.143e-11 
RG G GY 1.1 
RTCV 100 S 1e6  7.348e-04 -4.261e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 2655000u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 1.44e-05 NSUB = 6.841e+16 
+ KAPPA = 1.252e-02 NFS = 1.016e+10 
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 2.338e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 1.987e-08 TREF = 25 BV = 31 
+RS = 9.274e-03 N = 1.146e+00 IS = 1.935e-11 
+EG = 1.128e+00 XTI = 1.713e+00 TRS = 2.158e-03 
+CJO = 1.311e-10 VJ = 7.694e-01 M = 5.864e-01 ) 
.ENDS 
